1. Technical Field
This disclosure relates to a semiconductor device, and more particularly, to a small swing signal receiver and a semiconductor device including the same.
2. Description of the Related Art
In semiconductor devices, a level of an externally input signal may be different from a level of an internal signal. In this case, a signal receiver that receives the externally input signal and converts it into a higher level (for example, a complementary metal-oxide semiconductor (CMOS) level) is required. In addition, various signals need to be transmitted from a peripheral circuit to a core circuit or vice versa with semiconductor devices. Here, power consumption is high if a full-swing signal (e.g., a signal swinging between ground and a power supply voltage level) is transmitted. Accordingly, it is usual to transmit a small swing signal (hereinafter, referred to as a “small signal”) having a smaller swing amplitude (level) than the full-swing signal. A small signal receiver is required to receive the small signal.
However, when the design of a small signal receiver is not appropriate, reception characteristics are deteriorated. For example, a duty ratio of an input signal may deviate from a desired amount. In addition, current consumption of the signal receiver affects the entire power consumption of a semiconductor device. Such current consumption may come from leakage current in the small signal receiver.
FIGS. 1 and 2 are circuit diagrams of conventional signal receivers 10 and 20 for semiconductor devices.
The signal receiver 10 illustrated in FIG. 1 is a buffer type. The buffer-type signal receiver 10 includes two inverters 111 and 12 connected in series. Although not shown in detail, each of the inverters 11 and 12 usually includes a PMOS transistor and an NMOS transistor connected in series between a power supply and a ground. Since the PMOS transistor and the NMOS transistor operate in response to the same input signal, the two transistors may be turned on simultaneously at a level where the input signal transitions. Thus, a current path is formed from the power supply to the ground, increasing leakage current. As a result, the buffer-type signal receiver 10 has high current consumption due to leakage current.
The receiver 20 illustrated in FIG. 2 is a conventional level shifter. The level shifter 20 includes multiple NMOS transistors N1, N2, and N3; multiple PMOS transistors P1, P2, P3, and P4; and a buffer 22.
FIG. 5B illustrates signal waveforms of the level shifter 20 illustrated in FIG. 2. The operation of the level shifter 20 will be described with reference to FIGS. 2 and 5B below.
An input signal IN input to a node A1 is a small signal swinging between 0 V and 1V, as illustrated in FIG. 5B. A power supply voltage (VDD) is about 1.5 V.
When the input signal IN is at a high level, the first NMOS transistor N1 is turned on. As a result, the second PMOS transistor P2 is also turned on. In addition, the third NMOS transistor N3 is turned on, and therefore, the second NMOS N2 is turned off. Accordingly, a voltage at a node A2 transitions to a high level close to a VDD level. Thus an output signal OUT also transitions to a high level.
When the input signal IN is at a low level, the first and third NMOS transistors N1 and N3 are turned off and the third PMOS transistor P3 is turned on. Thus, the second NMOS transistor N2 is turned on. Accordingly, the voltage at the node A2 transitions to a low level and the output signal OUT also transitions to a low level. However, when the VDD is low, for example, when the VDD is lower than 1.5 V, the stack PMOS transistor P4 does not operate properly. In particular, when the input signal IN is at the low level, a voltage level of a signal input to a gate of the second NMOS transistor N2 is not sufficiently high and thus the second NMOS transistor N2 may not be turned on timely. For this reason, there may be a difference between a high level section and a low level section of the output signal OUT (expressed by an A3 graph in FIG. 5B).
The level shifter 20 illustrated in FIG. 2 has lower current consumption than the signal receiver 10 illustrated in FIG. 1 since leakage current is reduced. However, the level shifter 20 also has a problem in that a duty ratio is distorted in a low-voltage environment.